1.SoC system design and integration, team management
2.5+ years experience on digital IC design
3.Attractive staff benefits, bonus, share options
1.Key Tasks / Responsibilities
2.Take high level requirements and write chip or block level micro-architecture specifications.
3.Ability to undertake die-sizing, power estimation, technology selection etc to define an optimal solution for a given IC development.
4.Strong hands-on experience in RTL coding of modules, sub-system or full-chip (primarily Verilog or SystemVerilog)
5.Selection and integration of 3rd party IP into a SoC design
6.Ability to lead a digital team on a SoC project – mentoring and reviewing the work of colleagues and ensuring that code quality is at the highest level and consistent with coding guidelines and applicable quality processes.
7.Chip level integration and liaising with implementation and physical design staff to ensure that the RTL code is optimized and aligned with the requirements of the back-end team.
Key skills / Background
1.Ph.D or Master in Electronic Engineering, Computer Science or related discipline.
2.5+ year experience as a digital designer or digital lead in a number design of SoC developments.
3.A good understanding of the complete SoC flow from specification through to tape-out, validation and test.
4.Experience in system integration of main stream CPU cores, like ARM Cortex-M0, Cortex-M0+ etc.
5.Good working knowledge of verification techniques and methodologies and proven ability to debug issues in a structured and timely way.
6.Low power design expertise
1.Good knowledge of DFT techniques and the impact on the RTL design
2.Analog design knowledge or experience of working on mixed-signal SoC developments.
3.Extensive knowledge of verification methodologies particularly UVM and SystemVerilog.
4.Experience in the planning and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.
6.Experience of FPGA design and associated tools
1.Function block and system specification design；
2.RTL coding, design verification, logic synthesis, DFT and static timing analysis
3.System integration based on Cortex-M or RISC-V CPU core
1.Bachelor degree in Electronic Engineering or equivalent；
2.Knowledge in ASIC/FPGA design methodology；
3.Experience in one or more of the following areas is advantage；
4.Verilog based logic design, verification and synthesis；
5.Knowledge of low power logic design；
6.Knowledge of digital signal processing algorithm and its implementation
7.DFT, BIST, SCAN insertion, ATPG