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数字IC验证工程师
数字验证类
上海
2021.04.12
申请职位
申请职位
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岗位职责:
1.To develop test cases and/ or test framework;
2.To develop verification components using System Verilog;
3.To execute and debug test cases;
4.Working location:Shanghai.
岗位要求:
1.Bachelor's degree or above in Electrical Engineering, Computer Science, or equivalent education;
2.At-least 1 years of experience in UVM/OVM/VMM. System Verilog HVL;
3.Hands on experience of developing assertion, checkers, coverage and scenario creation;
4.Experience in developing test and coverage plan, Verification environment and validation plan;
5.Knowledge of at-least one industry standard protocols like SPI/DDR or similar is required;
6.Experience in scripting languages (Python, Perl, Linux Shell scripting etc.);
7.Experience with netlisting(modeling with skill language) is an advantage.
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